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tests: Add tests to create valid and invalid UART, I2C, SPI, CAN busses.
1 parent 17d9b50 commit 6d1ff7e

8 files changed

Lines changed: 70 additions & 1 deletion

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tests/pyb/can.py

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from pyb import CAN
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import pyb
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# test we can correctly create by id or name
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for bus in (-1, 0, 1, 2, 3, "YA", "YB", "YC"):
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try:
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CAN(bus, CAN.LOOPBACK)
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print("CAN", bus)
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except ValueError:
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print("ValueError", bus)
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CAN.initfilterbanks(14)
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can = CAN(1)
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print(can)

tests/pyb/can.py.exp

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ValueError -1
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ValueError 0
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CAN 1
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CAN 2
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ValueError 3
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CAN YA
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CAN YB
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ValueError YC
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CAN(1)
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CAN(1, CAN.LOOPBACK, extframe=False)
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False

tests/pyb/i2c.py

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@@ -1,8 +1,15 @@
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import pyb
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from pyb import I2C
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# test we can correctly create by id or name
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for bus in (-1, 0, 1, 2, 3, "X", "Y", "Z"):
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try:
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I2C(bus)
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print("I2C", bus)
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except ValueError:
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print("ValueError", bus)
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i2c = I2C(1)
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i2c2 = I2C(2)
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i2c.init(I2C.MASTER, baudrate=400000)
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print(i2c.scan())

tests/pyb/i2c.py.exp

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ValueError -1
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ValueError 0
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I2C 1
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I2C 2
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ValueError 3
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I2C X
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I2C Y
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ValueError Z
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[]
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[76]
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True

tests/pyb/spi.py

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,13 @@
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from pyb import SPI
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# test we can correctly create by id or name
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for bus in (-1, 0, 1, 2, 3, "X", "Y", "Z"):
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try:
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SPI(bus)
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print("SPI", bus)
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except ValueError:
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print("ValueError", bus)
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spi = SPI(1)
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print(spi)
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tests/pyb/spi.py.exp

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Original file line numberDiff line numberDiff line change
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ValueError -1
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ValueError 0
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SPI 1
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SPI 2
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ValueError 3
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SPI X
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SPI Y
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ValueError Z
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SPI(1)
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SPI(1, SPI.MASTER, baudrate=328125, prescaler=256, polarity=1, phase=0, bits=8)
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SPI(1, SPI.SLAVE, polarity=1, phase=1, bits=8)

tests/pyb/uart.py

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,13 @@
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from pyb import UART
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# test we can correctly create by id or name
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for bus in (-1, 0, 1, 2, 3, 4, 5, 6, 7, "XA", "XB", "YA", "YB", "Z"):
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try:
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UART(bus, 9600)
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print("UART", bus)
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except ValueError:
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print("ValueError", bus)
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uart = UART(1)
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uart = UART(1, 9600)
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uart = UART(1, 9600, bits=8, parity=None, stop=1)

tests/pyb/uart.py.exp

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Original file line numberDiff line numberDiff line change
@@ -1,3 +1,17 @@
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ValueError -1
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ValueError 0
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UART 1
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UART 2
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UART 3
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UART 4
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ValueError 5
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UART 6
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ValueError 7
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UART XA
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UART XB
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UART YA
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UART YB
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ValueError Z
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UART(1, baudrate=9600, bits=8, parity=None, stop=1, timeout=1000, timeout_char=0, read_buf_len=64)
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UART(1, baudrate=2400, bits=8, parity=None, stop=1, timeout=1000, timeout_char=0, read_buf_len=64)
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False

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